// ******************************************************************************
// Copyright     :  Copyright (C) 2020, Hisilicon Technologies Co. Ltd.
// File name     :  hva_smf_c_union_define.h
// Project line  :  Platform And Key Technologies Development
// Department    :  CAD Development Department
// Version       :  1.0
// Date          :  HVA_SMF
// Description   :  The description of xxx project
// Others        :  Generated automatically by nManager V5.1
// ******************************************************************************

#ifndef HVA_SMF_C_UNION_DEFINE_H
#define HVA_SMF_C_UNION_DEFINE_H

/* Define the union csr_hva_smf_fpga_ver_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 hva_smf_fpga_ver : 32; /* [31:0] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_hva_smf_fpga_ver_u;

/* Define the union csr_hva_smf_emu_ver_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 hva_smf_emu_ver : 32; /* [31:0] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_hva_smf_emu_ver_u;

/* Define the union csr_hva_smf_mem_attr_win0_l_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 hva_smf_mem_attr_win0_l : 32; /* [31:0] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_hva_smf_mem_attr_win0_l_u;

/* Define the union csr_hva_smf_mem_attr_win0_h_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 hva_smf_mem_attr_win0_h : 4; /* [3:0] */
        u32 rsv_0 : 28;                  /* [31:4] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_hva_smf_mem_attr_win0_h_u;

/* Define the union csr_hva_smf_mem_attr_win1_l_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 hva_smf_mem_attr_win1_l : 32; /* [31:0] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_hva_smf_mem_attr_win1_l_u;

/* Define the union csr_hva_smf_mem_attr_win1_h_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 hva_smf_mem_attr_win1_h : 4; /* [3:0] */
        u32 rsv_1 : 28;                  /* [31:4] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_hva_smf_mem_attr_win1_h_u;

/* Define the union csr_hva_smf_mem_attr_win2_l_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 hva_smf_mem_attr_win2_l : 32; /* [31:0] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_hva_smf_mem_attr_win2_l_u;

/* Define the union csr_hva_smf_mem_attr_win2_h_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 hva_smf_mem_attr_win2_h : 4; /* [3:0] */
        u32 rsv_2 : 28;                  /* [31:4] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_hva_smf_mem_attr_win2_h_u;

/* Define the union csr_hva_smf_mem_attr_win3_l_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 hva_smf_mem_attr_win3_l : 32; /* [31:0] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_hva_smf_mem_attr_win3_l_u;

/* Define the union csr_hva_smf_mem_attr_win3_h_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 hva_smf_mem_attr_win3_h : 4; /* [3:0] */
        u32 rsv_3 : 28;                  /* [31:4] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_hva_smf_mem_attr_win3_h_u;

/* Define the union csr_hva_smf_mem_attr_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 hva_smf_mem_attr_rd : 5; /* [4:0] */
        u32 rsv_4 : 3;               /* [7:5] */
        u32 hva_smf_mem_attr_wr : 5; /* [12:8] */
        u32 rsv_5 : 19;              /* [31:13] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_hva_smf_mem_attr_u;

/* Define the union csr_hva_smf_ar_cfg_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 hva_smf_cfg_arqos_set : 4;     /* [3:0] */
        u32 hva_smf_cfg_arssv_set : 1;     /* [4] */
        u32 hva_smf_cfg_arstrmid_mode : 1; /* [5] */
        u32 rsv_6 : 2;                     /* [7:6] */
        u32 hva_smf_cfg_rdcln_thrld : 4;   /* [11:8] */
        u32 hva_smf_cfg_rdfna_thrld : 4;   /* [15:12] */
        u32 hva_smf_cfg_rdtype_thrld : 4;  /* [19:16] */
        u32 hva_smf_cfg_rdfa_thrld : 4;    /* [23:20] */
        u32 hva_smf_cfg_rd_fa_mode : 2;    /* [25:24] */
        u32 hva_smf_cfg_rd_fna_mode : 2;   /* [27:26] */
        u32 hva_smf_cfg_rd_cln_mode : 1;   /* [28] */
        u32 hva_smf_cfg_rd_type_mode : 1;  /* [29] */
        u32 rsv_7 : 2;                     /* [31:30] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_hva_smf_ar_cfg_u;

/* Define the union csr_hva_smf_wr_cfg_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 hva_smf_cfg_awqos_set : 4;     /* [3:0] */
        u32 hva_smf_cfg_awssv_set : 1;     /* [4] */
        u32 hva_smf_cfg_awstrmid_mode : 1; /* [5] */
        u32 rsv_8 : 2;                     /* [7:6] */
        u32 hva_smf_cfg_wr_so_set : 4;     /* [11:8] */
        u32 hva_smf_cfg_wrfna_thrld : 4;   /* [15:12] */
        u32 hva_smf_cfg_wrtype_thrld : 4;  /* [19:16] */
        u32 hva_smf_cfg_wrfa_thrld : 4;    /* [23:20] */
        u32 hva_smf_cfg_wr_fa_mode : 2;    /* [25:24] */
        u32 hva_smf_cfg_wr_fna_mode : 2;   /* [27:26] */
        u32 hva_smf_cfg_wr_fp_mode : 2;    /* [29:28] */
        u32 hva_smf_cfg_wr_type_mode : 1;  /* [30] */
        u32 hva_smf_cfg_wr_so_mode : 1;    /* [31] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_hva_smf_wr_cfg_u;

/* Define the union csr_hva_smf_arstrmid_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 hva_smf_rd_strmid : 32; /* [31:0] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_hva_smf_arstrmid_u;

/* Define the union csr_hva_smf_awstrmid_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 hva_smf_wr_strmid : 32; /* [31:0] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_hva_smf_awstrmid_u;

/* Define the union csr_hva_smf_pf_cmd_type_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 hva_smf_cfg_pf_cmd_type : 16; /* [15:0] */
        u32 rsv_9 : 16;                   /* [31:16] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_hva_smf_pf_cmd_type_u;

/* Define the union csr_hva_smf_int_starus_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 hva_smf_npq_ov_int_status : 1;         /* [0] */
        u32 hva_smf_npq_uf_int_status : 1;         /* [1] */
        u32 hva_smf_npq_send_empty_int_status : 1; /* [2] */
        u32 hva_smf_pq_ov_int_status : 1;          /* [3] */
        u32 hva_smf_pq_uf_int_status : 1;          /* [4] */
        u32 hva_smf_pq_send_empty_int_status : 1;  /* [5] */
        u32 hva_smf_1bit_ecc_int_status : 1;       /* [6] */
        u32 hva_smf_2bit_ecc_int_status : 1;       /* [7] */
        u32 hva_cpth_fifo_ov_int_status : 1;       /* [8] */
        u32 rsv_10 : 23;                           /* [31:9] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_hva_smf_int_starus_u;

/* Define the union csr_hva_smf_int_en_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 hva_smf_npq_ov_int_en : 1;         /* [0] */
        u32 hva_smf_npq_uf_int_en : 1;         /* [1] */
        u32 hva_smf_npq_send_empty_int_en : 1; /* [2] */
        u32 hva_smf_pq_ov_int_en : 1;          /* [3] */
        u32 hva_smf_pq_uf_int_en : 1;          /* [4] */
        u32 hva_smf_pq_send_empty_int_en : 1;  /* [5] */
        u32 hva_smf_1bit_ecc_int_en : 1;       /* [6] */
        u32 hva_smf_2bit_ecc_int_en : 1;       /* [7] */
        u32 hva_cpth_fifo_ov_int_en : 1;       /* [8] */
        u32 rsv_11 : 23;                       /* [31:9] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_hva_smf_int_en_u;

/* Define the union csr_hva_smf_int_set_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 hva_smf_npq_ov_int_set : 1;         /* [0] */
        u32 hva_smf_npq_uf_int_set : 1;         /* [1] */
        u32 hva_smf_npq_send_empty_int_set : 1; /* [2] */
        u32 hva_smf_pq_ov_int_set : 1;          /* [3] */
        u32 hva_smf_pq_uf_int_set : 1;          /* [4] */
        u32 hva_smf_pq_send_empty_int_set : 1;  /* [5] */
        u32 hva_smf_1bit_ecc_int_set : 1;       /* [6] */
        u32 hva_smf_2bit_ecc_int_set : 1;       /* [7] */
        u32 hva_cpth_fifo_ov_int_set : 1;       /* [8] */
        u32 rsv_12 : 23;                        /* [31:9] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_hva_smf_int_set_u;

/* Define the union csr_hva_smf_int_raw_status_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 hva_smf_npq_ov_int_raw_status : 1;         /* [0] */
        u32 hva_smf_npq_uf_int_raw_status : 1;         /* [1] */
        u32 hva_smf_npq_send_empty_int_raw_status : 1; /* [2] */
        u32 hva_smf_pq_ov_int_raw_status : 1;          /* [3] */
        u32 hva_smf_pq_uf_int_raw_status : 1;          /* [4] */
        u32 hva_smf_pq_send_empty_int_raw_status : 1;  /* [5] */
        u32 hva_smf_1bit_ecc_int_raw_status : 1;       /* [6] */
        u32 hva_smf_2bit_ecc_int_raw_status : 1;       /* [7] */
        u32 hva_cpth_fifo_ov_int_raw_status : 1;       /* [8] */
        u32 rsv_13 : 23;                               /* [31:9] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_hva_smf_int_raw_status_u;

/* Define the union csr_hva_icl_cfg_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 sc_dispatch_errrsp : 1; /* [0] */
        u32 rsv_14 : 15;            /* [15:1] */
        u32 hva_icl_smmu_bdf : 16;  /* [31:16] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_hva_icl_cfg_u;

/* Define the union csr_hva_smf_axi_max_trans_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 hva_smf_cfg_rd_max_trans : 8; /* [7:0] */
        u32 hva_smf_cfg_wr_max_trans : 8; /* [15:8] */
        u32 rsv_15 : 16;                  /* [31:16] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_hva_smf_axi_max_trans_u;

/* Define the union csr_hva_smf_cpi_cfg_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 hva_smf_cpi_10bit_tag_req_en : 1;  /* [0] */
        u32 hva_smf_cpi_10bit_tag_cpl_en : 1;  /* [1] */
        u32 hva_smf_cpi_extended_tag_en : 1;   /* [2] */
        u32 hva_smf_cpi_cpl_timeout_dis : 1;   /* [3] */
        u32 hva_smf_cpi_cpl_timeout_value : 4; /* [7:4] */
        u32 hva_smf_cpi_cfg_mrrs : 3;          /* [10:8] */
        u32 rsv_16 : 1;                        /* [11] */
        u32 hva_smf_cpi_cfg_mps : 3;           /* [14:12] */
        u32 rsv_17 : 1;                        /* [15] */
        u32 hva_smf_link_down : 1;             /* [16] */
        u32 hva_smf_cpi_tx_crd_active_en : 1;  /* [17] */
        u32 rsv_18 : 14;                       /* [31:18] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_hva_smf_cpi_cfg_u;

/* Define the union csr_hva_smf_cpi_crdt_cfg_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 hva_smf_cpi_p_hed_crdt : 8;  /* [7:0] */
        u32 hva_smf_cpi_p_dat_crdt : 8;  /* [15:8] */
        u32 hva_smf_cpi_np_hed_crdt : 8; /* [23:16] */
        u32 rsv_19 : 7;                  /* [30:24] */
        u32 hva_smf_cpi_crdt_init : 1;   /* [31] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_hva_smf_cpi_crdt_cfg_u;

/* Define the union csr_hva_smf_ram_ecc_bypass_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 hva_smf_ram_err_chk_bypass : 1; /* [0] */
        u32 rsv_20 : 31;                    /* [31:1] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_hva_smf_ram_ecc_bypass_u;

/* Define the union csr_hva_smf_ram_ecc_err_ins_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 hva_smf_npq_db_ram_cerr_ins_req : 1;     /* [0] */
        u32 hva_smf_npq_db_ram_ucerr_ins_req : 1;    /* [1] */
        u32 hva_smf_pq_db_ram_cerr_ins_req : 1;      /* [2] */
        u32 hva_smf_pq_db_ram_ucerr_ins_req : 1;     /* [3] */
        u32 hva_smf_npq_entry_ram_cerr_ins_req : 1;  /* [4] */
        u32 hva_smf_npq_entry_ram_ucerr_ins_req : 1; /* [5] */
        u32 hva_smf_pq_entry_ram_cerr_ins_req : 1;   /* [6] */
        u32 hva_smf_pq_entry_ram_ucerr_ins_req : 1;  /* [7] */
        u32 hva_cpth_fifo_ram_cerr_ins_req : 1;      /* [8] */
        u32 hva_cpth_fifo_ram_ucerr_ins_req : 1;     /* [9] */
        u32 rsv_21 : 22;                             /* [31:10] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_hva_smf_ram_ecc_err_ins_u;

/* Define the union csr_hva_smf_fatal_err_ctrl_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 hva_smf_npq_db_ram_ucerr_fatal_en : 1;    /* [0] */
        u32 hva_smf_pq_db_ram_ucerr_fatal_en : 1;     /* [1] */
        u32 hva_smf_npq_entry_ram_ucerr_fatal_en : 1; /* [2] */
        u32 hva_smf_pq_entry_ram_ucerr_fatal_en : 1;  /* [3] */
        u32 hva_smf_npq_ov_fatal_en : 1;              /* [4] */
        u32 hva_smf_npq_uf_fatal_en : 1;              /* [5] */
        u32 hva_smf_npq_send_empty_fatal_en : 1;      /* [6] */
        u32 hva_smf_pq_ov_fatal_en : 1;               /* [7] */
        u32 hva_smf_pq_uf_fatal_en : 1;               /* [8] */
        u32 hva_smf_pq_send_empty_fatal_en : 1;       /* [9] */
        u32 hva_cpth_fifo_ram_ucerr_fatal_en : 1;     /* [10] */
        u32 hva_cpth_fifo_ov_fatal_en : 1;            /* [11] */
        u32 rsv_22 : 19;                              /* [30:12] */
        u32 hva_smf_fatal_err_en : 1;                 /* [31] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_hva_smf_fatal_err_ctrl_u;

/* Define the union csr_hva_smf_inner_crdt_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 hva_smf_inner_cpl_data_crdt : 3; /* [2:0] */
        u32 rsv_23 : 1;                      /* [3] */
        u32 hva_smf_inner_send_npq_crdt : 3; /* [6:4] */
        u32 rsv_24 : 1;                      /* [7] */
        u32 hva_smf_inner_send_pq_crdt : 3;  /* [10:8] */
        u32 rsv_25 : 20;                     /* [30:11] */
        u32 hva_smf_inner_crdt_init : 1;     /* [31] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_hva_smf_inner_crdt_u;

/* Define the union csr_hva_smf_fifo_af_cfg_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 hva_smf_pq_sdata_fifo_af_th : 4; /* [3:0] */
        u32 rsv_26 : 28;                     /* [31:4] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_hva_smf_fifo_af_cfg_u;

/* Define the union csr_hva_smf_crdt_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 hva_smf_rsp_crdt : 5;  /* [4:0] */
        u32 rsv_27 : 3;            /* [7:5] */
        u32 hva_smf_cpl_crdt : 3;  /* [10:8] */
        u32 rsv_28 : 5;            /* [15:11] */
        u32 hva_smf_crdt_init : 1; /* [16] */
        u32 rsv_29 : 15;           /* [31:17] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_hva_smf_crdt_u;

/* Define the union csr_hva_smf_pnp_odr_dis_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 hva_cpth_pnp_odr_dis : 1; /* [0] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_hva_smf_pnp_odr_dis_u;

/* Define the union csr_hva_smf_dfx_cfg_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 hva_smf_dfx_tx_cpl_stat_en : 1;        /* [0] */
        u32 hva_smf_dfx_tx_cpl_stat_clr : 1;       /* [1] */
        u32 hva_smf_dfx_tx_cpl_cnt_clr : 1;        /* [2] */
        u32 hva_smf_dfx_hva_get_cpi_p_cnt_clr : 1; /* [3] */
        u32 hva_smf_dfx_tx_p_stat_en : 1;          /* [4] */
        u32 hva_smf_dfx_tx_p_stat_clr : 1;         /* [5] */
        u32 hva_smf_dfx_ucerr_cnt_clr : 1;         /* [6] */
        u32 hva_smf_dfx_cerr_cnt_clr : 1;          /* [7] */
        u32 rsv_30 : 24;                           /* [31:8] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_hva_smf_dfx_cfg_u;

/* Define the union csr_hva_smf_dfx_cpl_bw0_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 hva_smf_dfx_tx_cpl_bw_curr : 16; /* [15:0] */
        u32 hva_smf_dfx_tx_cpl_bw_max : 16;  /* [31:16] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_hva_smf_dfx_cpl_bw0_u;

/* Define the union csr_hva_smf_dfx_cpl_bw1_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 hva_smf_dfx_tx_cpl_bw_ava : 16; /* [15:0] */
        u32 rsv_31 : 16;                    /* [31:16] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_hva_smf_dfx_cpl_bw1_u;

/* Define the union csr_hva_smf_dfx_npq_db_state_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 hva_smf_dfx_npq_db_state : 32; /* [31:0] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_hva_smf_dfx_npq_db_state_u;

/* Define the union csr_hva_smf_dfx_tx_cpl_cnt0_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 hva_smf_dfx_tx_cpl_dat_err_cnt : 16;   /* [15:0] */
        u32 hva_smf_dfx_tx_cpl_unsuccess_cnt : 16; /* [31:16] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_hva_smf_dfx_tx_cpl_cnt0_u;

/* Define the union csr_hva_smf_dfx_tx_cpl_cnt1_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 hva_smf_dfx_tx_cpl_cnt : 32; /* [31:0] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_hva_smf_dfx_tx_cpl_cnt1_u;

/* Define the union csr_hva_smf_npq_ptr_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 hva_smf_dfx_npq_send_ptr : 8; /* [7:0] */
        u32 hva_smf_dfx_npq_free_ptr : 8; /* [15:8] */
        u32 hva_smf_dfx_npq_rls_ptr : 8;  /* [23:16] */
        u32 hva_smf_dfx_npq_free_cnt : 8; /* [31:24] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_hva_smf_npq_ptr_u;

/* Define the union csr_hva_smf_dfx_p_bw0_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 hva_smf_dfx_tx_p_bw_curr : 16; /* [15:0] */
        u32 hva_smf_dfx_tx_p_bw_max : 16;  /* [31:16] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_hva_smf_dfx_p_bw0_u;

/* Define the union csr_hva_smf_dfx_p_bw1_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 hva_smf_dfx_tx_p_bw_ava : 16; /* [15:0] */
        u32 rsv_32 : 16;                  /* [31:16] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_hva_smf_dfx_p_bw1_u;

/* Define the union csr_hva_smf_dfx_p_cnt_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 hva_smf_dfx_hva_get_cpi_p_cnt : 16; /* [15:0] */
        u32 rsv_33 : 16;                        /* [31:16] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_hva_smf_dfx_p_cnt_u;

/* Define the union csr_hva_smf_dfx_pq_ptr_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 hva_smf_dfx_pq_send_ptr : 8; /* [7:0] */
        u32 hva_smf_dfx_pq_free_ptr : 8; /* [15:8] */
        u32 hva_smf_dfx_pq_rls_ptr : 8;  /* [23:16] */
        u32 hva_smf_dfx_pq_free_cnt : 8; /* [31:24] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_hva_smf_dfx_pq_ptr_u;

/* Define the union csr_hva_smf_dfx_pq_wr_err_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 rsv_34 : 16;                      /* [15:0] */
        u32 hva_smf_dfx_pq_wr_err_abresp : 1; /* [16] */
        u32 hva_smf_dfx_pq_wr_err : 1;        /* [17] */
        u32 hva_smf_dfx_pq_wr_err_clr : 1;    /* [18] */
        u32 rsv_35 : 13;                      /* [31:19] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_hva_smf_dfx_pq_wr_err_u;

/* Define the union csr_hva_smf_dfx_pq_wr_err_addr_h_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 hva_smf_dfx_pq_wr_err_addr_h : 32; /* [31:0] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_hva_smf_dfx_pq_wr_err_addr_h_u;

/* Define the union csr_hva_smf_dfx_pq_wr_err_addr_l_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 hva_smf_dfx_pq_wr_err_addr_l : 32; /* [31:0] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_hva_smf_dfx_pq_wr_err_addr_l_u;

/* Define the union csr_hva_smf_dfx_tlp_zero_len_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 hva_smf_dfx_pq_zero_write : 1; /* [0] */
        u32 hva_smf_dfx_npq_zero_read : 1; /* [1] */
        u32 rsv_36 : 30;                   /* [31:2] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_hva_smf_dfx_tlp_zero_len_u;

/* Define the union csr_hva_smf_dfx_axi_bid_err_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 hva_smf_dfx_hva_bid_err : 1; /* [0] */
        u32 rsv_37 : 31;                 /* [31:1] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_hva_smf_dfx_axi_bid_err_u;

/* Define the union csr_hva_smf_dfx_db_ecc_err_addr_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 hva_smf_dfx_pq_db_ecc_err_addr : 5;  /* [4:0] */
        u32 rsv_38 : 11;                         /* [15:5] */
        u32 hva_smf_dfx_npq_db_ecc_err_addr : 9; /* [24:16] */
        u32 rsv_39 : 7;                          /* [31:25] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_hva_smf_dfx_db_ecc_err_addr_u;

/* Define the union csr_hva_smf_dfx_entry_ecc_err_addr_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 hva_smf_dfx_pq_entry_ecc_err_addr : 7;  /* [6:0] */
        u32 rsv_40 : 1;                             /* [7] */
        u32 hva_smf_dfx_npq_entry_ecc_err_addr : 7; /* [14:8] */
        u32 rsv_41 : 1;                             /* [15] */
        u32 hva_smf_dfx_cpth_fifo_ecc_err_addr : 6; /* [21:16] */
        u32 rsv_42 : 10;                            /* [31:22] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_hva_smf_dfx_entry_ecc_err_addr_u;

/* Define the union csr_hva_smf_dfx_mem_cerr_cnt_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 hva_smf_dfx_mem_cerr_cnt : 32; /* [31:0] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_hva_smf_dfx_mem_cerr_cnt_u;

/* Define the union csr_hva_smf_dfx_mem_ucerr_cnt_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 hva_smf_dfx_mem_ucerr_cnt : 32; /* [31:0] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_hva_smf_dfx_mem_ucerr_cnt_u;

/* Define the union csr_hva_smf_dfx_ecc_sta_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 hva_smf_npq_db_ram_cerr : 1;     /* [0] */
        u32 hva_smf_npq_db_ram_ucerr : 1;    /* [1] */
        u32 hva_smf_pq_db_ram_cerr : 1;      /* [2] */
        u32 hva_smf_pq_db_ram_ucerr : 1;     /* [3] */
        u32 hva_smf_npq_entry_ram_cerr : 1;  /* [4] */
        u32 hva_smf_npq_entry_ram_ucerr : 1; /* [5] */
        u32 hva_smf_pq_entry_ram_cerr : 1;   /* [6] */
        u32 hva_smf_pq_entry_ram_ucerr : 1;  /* [7] */
        u32 hva_cpth_fifo_ram_cerr : 1;      /* [8] */
        u32 hva_cpth_fifo_ram_ucerr : 1;     /* [9] */
        u32 rsv_43 : 22;                     /* [31:10] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_hva_smf_dfx_ecc_sta_u;

/* Define the union csr_hva_smf_mem_ctrl_bus_0_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 hva_smf_mem_ctrl_bus_0 : 32; /* [31:0] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_hva_smf_mem_ctrl_bus_0_u;

/* Define the union csr_hva_smf_mem_ctrl_bus_1_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 hva_smf_mem_ctrl_bus_1 : 32; /* [31:0] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_hva_smf_mem_ctrl_bus_1_u;

/* Define the union csr_hva_smf_mem_ctrl_bus_2_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 hva_smf_mem_ctrl_bus_2 : 32; /* [31:0] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_hva_smf_mem_ctrl_bus_2_u;

/* Define the union csr_hva_smf_mem_ctrl_bus_3_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 hva_smf_mem_ctrl_bus_3 : 32; /* [31:0] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_hva_smf_mem_ctrl_bus_3_u;

/* Define the union csr_hva_smf_mem_ctrl_bus_4_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 hva_smf_mem_ctrl_bus_4 : 6; /* [5:0] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_hva_smf_mem_ctrl_bus_4_u;

/* Define the union csr_smf_hva_req_api_num_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 dfx_smf_hva_wr_requs_cnt : 16; /* [15:0] */
        u32 dfx_smf_hva_rd_requs_cnt : 16; /* [31:16] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_smf_hva_req_api_num_u;

/* Define the union csr_hva_smf_rsp_api_num_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 dfx_hva_smf_rd_rsp_cnt : 16; /* [15:0] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_hva_smf_rsp_api_num_u;

/* Define the union csr_hva_smf_smmu_axi_rd_num_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 dfx_smmu_hva_rl_cnt : 16; /* [15:0] */
        u32 dfx_hva_smmu_ar_cnt : 16; /* [31:16] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_hva_smf_smmu_axi_rd_num_u;

/* Define the union csr_hva_smf_smmu_axi_wr_num_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 dfx_hva_smmu_wl_cnt : 16; /* [15:0] */
        u32 dfx_hva_smmu_aw_cnt : 16; /* [31:16] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_hva_smf_smmu_axi_wr_num_u;

/* Define the union csr_smmu_hva_axi_b_num_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 dfx_smmu_hva_b_cnt : 16; /* [15:0] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_smmu_hva_axi_b_num_u;

/* Define the union csr_hva_smf_lat_sts_cfg_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 cfg_lat_stat_clr : 1; /* [0] */
        u32 cfg_lat_stat_en : 1;  /* [1] */
        u32 rsv_44 : 30;          /* [31:2] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_hva_smf_lat_sts_cfg_u;

/* Define the union csr_hva_smf_wr_bp_cfg_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 cfg_wr_bp_clr_th : 16; /* [15:0] */
        u32 cfg_wr_bp_th : 16;     /* [31:16] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_hva_smf_wr_bp_cfg_u;

/* Define the union csr_hva_smf_rd_bp_cfg_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 cfg_rd_bp_clr_th : 16; /* [15:0] */
        u32 cfg_rd_bp_th : 16;     /* [31:16] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_hva_smf_rd_bp_cfg_u;

/* Define the union csr_hva_jam_time_cfg_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 cfg_jam_bp_bus_timer : 32; /* [31:0] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_hva_jam_time_cfg_u;


// ==============================================================================
/* Define the global struct */
typedef struct {
    volatile csr_hva_smf_fpga_ver_u hva_smf_fpga_ver;                                /* 0 */
    volatile csr_hva_smf_emu_ver_u hva_smf_emu_ver;                                  /* 4 */
    volatile csr_hva_smf_mem_attr_win0_l_u hva_smf_mem_attr_win0_l;                  /* C */
    volatile csr_hva_smf_mem_attr_win0_h_u hva_smf_mem_attr_win0_h;                  /* 10 */
    volatile csr_hva_smf_mem_attr_win1_l_u hva_smf_mem_attr_win1_l;                  /* 14 */
    volatile csr_hva_smf_mem_attr_win1_h_u hva_smf_mem_attr_win1_h;                  /* 18 */
    volatile csr_hva_smf_mem_attr_win2_l_u hva_smf_mem_attr_win2_l;                  /* 1C */
    volatile csr_hva_smf_mem_attr_win2_h_u hva_smf_mem_attr_win2_h;                  /* 20 */
    volatile csr_hva_smf_mem_attr_win3_l_u hva_smf_mem_attr_win3_l;                  /* 24 */
    volatile csr_hva_smf_mem_attr_win3_h_u hva_smf_mem_attr_win3_h;                  /* 28 */
    volatile csr_hva_smf_mem_attr_u hva_smf_mem_attr[5];                             /* 30 */
    volatile csr_hva_smf_ar_cfg_u hva_smf_ar_cfg;                                    /* 50 */
    volatile csr_hva_smf_wr_cfg_u hva_smf_wr_cfg;                                    /* 54 */
    volatile csr_hva_smf_arstrmid_u hva_smf_arstrmid;                                /* 58 */
    volatile csr_hva_smf_awstrmid_u hva_smf_awstrmid;                                /* 5C */
    volatile csr_hva_smf_pf_cmd_type_u hva_smf_pf_cmd_type;                          /* 7C */
    volatile csr_hva_smf_int_starus_u hva_smf_int_starus;                            /* 80 */
    volatile csr_hva_smf_int_en_u hva_smf_int_en;                                    /* 84 */
    volatile csr_hva_smf_int_set_u hva_smf_int_set;                                  /* 88 */
    volatile csr_hva_smf_int_raw_status_u hva_smf_int_raw_status;                    /* 8C */
    volatile csr_hva_icl_cfg_u hva_icl_cfg;                                          /* 90 */
    volatile csr_hva_smf_axi_max_trans_u hva_smf_axi_max_trans;                      /* A0 */
    volatile csr_hva_smf_cpi_cfg_u hva_smf_cpi_cfg;                                  /* B0 */
    volatile csr_hva_smf_cpi_crdt_cfg_u hva_smf_cpi_crdt_cfg;                        /* B4 */
    volatile csr_hva_smf_ram_ecc_bypass_u hva_smf_ram_ecc_bypass;                    /* B8 */
    volatile csr_hva_smf_ram_ecc_err_ins_u hva_smf_ram_ecc_err_ins;                  /* BC */
    volatile csr_hva_smf_fatal_err_ctrl_u hva_smf_fatal_err_ctrl;                    /* C0 */
    volatile csr_hva_smf_inner_crdt_u hva_smf_inner_crdt;                            /* C4 */
    volatile csr_hva_smf_fifo_af_cfg_u hva_smf_fifo_af_cfg;                          /* C8 */
    volatile csr_hva_smf_crdt_u hva_smf_crdt;                                        /* CC */
    volatile csr_hva_smf_pnp_odr_dis_u hva_smf_pnp_odr_dis;                          /* D0 */
    volatile csr_hva_smf_dfx_cfg_u hva_smf_dfx_cfg;                                  /* 200 */
    volatile csr_hva_smf_dfx_cpl_bw0_u hva_smf_dfx_cpl_bw0[4];                       /* 210 */
    volatile csr_hva_smf_dfx_cpl_bw1_u hva_smf_dfx_cpl_bw1[4];                       /* 220 */
    volatile csr_hva_smf_dfx_npq_db_state_u hva_smf_dfx_npq_db_state[4];             /* 230 */
    volatile csr_hva_smf_dfx_tx_cpl_cnt0_u hva_smf_dfx_tx_cpl_cnt0[4];               /* 240 */
    volatile csr_hva_smf_dfx_tx_cpl_cnt1_u hva_smf_dfx_tx_cpl_cnt1[4];               /* 250 */
    volatile csr_hva_smf_npq_ptr_u hva_smf_npq_ptr[4];                               /* 260 */
    volatile csr_hva_smf_dfx_p_bw0_u hva_smf_dfx_p_bw0[4];                           /* 270 */
    volatile csr_hva_smf_dfx_p_bw1_u hva_smf_dfx_p_bw1[4];                           /* 280 */
    volatile csr_hva_smf_dfx_p_cnt_u hva_smf_dfx_p_cnt[4];                           /* 290 */
    volatile csr_hva_smf_dfx_pq_ptr_u hva_smf_dfx_pq_ptr[4];                         /* 2A0 */
    volatile csr_hva_smf_dfx_pq_wr_err_u hva_smf_dfx_pq_wr_err[4];                   /* 2B0 */
    volatile csr_hva_smf_dfx_pq_wr_err_addr_h_u hva_smf_dfx_pq_wr_err_addr_h[4];     /* 2C0 */
    volatile csr_hva_smf_dfx_pq_wr_err_addr_l_u hva_smf_dfx_pq_wr_err_addr_l[4];     /* 2D0 */
    volatile csr_hva_smf_dfx_tlp_zero_len_u hva_smf_dfx_tlp_zero_len;                /* 2E0 */
    volatile csr_hva_smf_dfx_axi_bid_err_u hva_smf_dfx_axi_bid_err;                  /* 2F0 */
    volatile csr_hva_smf_dfx_db_ecc_err_addr_u hva_smf_dfx_db_ecc_err_addr[4];       /* 300 */
    volatile csr_hva_smf_dfx_entry_ecc_err_addr_u hva_smf_dfx_entry_ecc_err_addr[4]; /* 310 */
    volatile csr_hva_smf_dfx_mem_cerr_cnt_u hva_smf_dfx_mem_cerr_cnt[4];             /* 320 */
    volatile csr_hva_smf_dfx_mem_ucerr_cnt_u hva_smf_dfx_mem_ucerr_cnt[4];           /* 330 */
    volatile csr_hva_smf_dfx_ecc_sta_u hva_smf_dfx_ecc_sta[4];                       /* 340 */
    volatile csr_hva_smf_mem_ctrl_bus_0_u hva_smf_mem_ctrl_bus_0;                    /* 350 */
    volatile csr_hva_smf_mem_ctrl_bus_1_u hva_smf_mem_ctrl_bus_1;                    /* 354 */
    volatile csr_hva_smf_mem_ctrl_bus_2_u hva_smf_mem_ctrl_bus_2;                    /* 358 */
    volatile csr_hva_smf_mem_ctrl_bus_3_u hva_smf_mem_ctrl_bus_3;                    /* 35C */
    volatile csr_hva_smf_mem_ctrl_bus_4_u hva_smf_mem_ctrl_bus_4;                    /* 360 */
    volatile csr_smf_hva_req_api_num_u smf_hva_req_api_num[4];                       /* 370 */
    volatile csr_hva_smf_rsp_api_num_u hva_smf_rsp_api_num[4];                       /* 380 */
    volatile csr_hva_smf_smmu_axi_rd_num_u hva_smf_smmu_axi_rd_num;                  /* 390 */
    volatile csr_hva_smf_smmu_axi_wr_num_u hva_smf_smmu_axi_wr_num;                  /* 394 */
    volatile csr_smmu_hva_axi_b_num_u smmu_hva_axi_b_num;                            /* 398 */
    volatile csr_hva_smf_lat_sts_cfg_u hva_smf_lat_sts_cfg;                          /* 400 */
    volatile csr_hva_smf_wr_bp_cfg_u hva_smf_wr_bp_cfg;                              /* 404 */
    volatile csr_hva_smf_rd_bp_cfg_u hva_smf_rd_bp_cfg;                              /* 408 */
    volatile csr_hva_jam_time_cfg_u hva_jam_time_cfg;                                /* 40C */
} S_hva_smf_reg_REGS_TYPE;

/* Declare the struct pointor of the module hva_smf_reg */
extern volatile S_hva_smf_reg_REGS_TYPE *gophva_smf_regAllReg;

/* Declare the functions that set the member value */
int iSetHVA_SMF_FPGA_VER_hva_smf_fpga_ver(unsigned int uhva_smf_fpga_ver);
int iSetHVA_SMF_EMU_VER_hva_smf_emu_ver(unsigned int uhva_smf_emu_ver);
int iSetHVA_SMF_MEM_ATTR_WIN0_L_hva_smf_mem_attr_win0_l(unsigned int uhva_smf_mem_attr_win0_l);
int iSetHVA_SMF_MEM_ATTR_WIN0_H_hva_smf_mem_attr_win0_h(unsigned int uhva_smf_mem_attr_win0_h);
int iSetHVA_SMF_MEM_ATTR_WIN1_L_hva_smf_mem_attr_win1_l(unsigned int uhva_smf_mem_attr_win1_l);
int iSetHVA_SMF_MEM_ATTR_WIN1_H_hva_smf_mem_attr_win1_h(unsigned int uhva_smf_mem_attr_win1_h);
int iSetHVA_SMF_MEM_ATTR_WIN2_L_hva_smf_mem_attr_win2_l(unsigned int uhva_smf_mem_attr_win2_l);
int iSetHVA_SMF_MEM_ATTR_WIN2_H_hva_smf_mem_attr_win2_h(unsigned int uhva_smf_mem_attr_win2_h);
int iSetHVA_SMF_MEM_ATTR_WIN3_L_hva_smf_mem_attr_win3_l(unsigned int uhva_smf_mem_attr_win3_l);
int iSetHVA_SMF_MEM_ATTR_WIN3_H_hva_smf_mem_attr_win3_h(unsigned int uhva_smf_mem_attr_win3_h);
int iSetHVA_SMF_MEM_ATTR_hva_smf_mem_attr_rd(unsigned int uhva_smf_mem_attr_rd);
int iSetHVA_SMF_MEM_ATTR_hva_smf_mem_attr_wr(unsigned int uhva_smf_mem_attr_wr);
int iSetHVA_SMF_AR_CFG_hva_smf_cfg_arqos_set(unsigned int uhva_smf_cfg_arqos_set);
int iSetHVA_SMF_AR_CFG_hva_smf_cfg_arssv_set(unsigned int uhva_smf_cfg_arssv_set);
int iSetHVA_SMF_AR_CFG_hva_smf_cfg_arstrmid_mode(unsigned int uhva_smf_cfg_arstrmid_mode);
int iSetHVA_SMF_AR_CFG_hva_smf_cfg_rdcln_thrld(unsigned int uhva_smf_cfg_rdcln_thrld);
int iSetHVA_SMF_AR_CFG_hva_smf_cfg_rdfna_thrld(unsigned int uhva_smf_cfg_rdfna_thrld);
int iSetHVA_SMF_AR_CFG_hva_smf_cfg_rdtype_thrld(unsigned int uhva_smf_cfg_rdtype_thrld);
int iSetHVA_SMF_AR_CFG_hva_smf_cfg_rdfa_thrld(unsigned int uhva_smf_cfg_rdfa_thrld);
int iSetHVA_SMF_AR_CFG_hva_smf_cfg_rd_fa_mode(unsigned int uhva_smf_cfg_rd_fa_mode);
int iSetHVA_SMF_AR_CFG_hva_smf_cfg_rd_fna_mode(unsigned int uhva_smf_cfg_rd_fna_mode);
int iSetHVA_SMF_AR_CFG_hva_smf_cfg_rd_cln_mode(unsigned int uhva_smf_cfg_rd_cln_mode);
int iSetHVA_SMF_AR_CFG_hva_smf_cfg_rd_type_mode(unsigned int uhva_smf_cfg_rd_type_mode);
int iSetHVA_SMF_WR_CFG_hva_smf_cfg_awqos_set(unsigned int uhva_smf_cfg_awqos_set);
int iSetHVA_SMF_WR_CFG_hva_smf_cfg_awssv_set(unsigned int uhva_smf_cfg_awssv_set);
int iSetHVA_SMF_WR_CFG_hva_smf_cfg_awstrmid_mode(unsigned int uhva_smf_cfg_awstrmid_mode);
int iSetHVA_SMF_WR_CFG_hva_smf_cfg_wr_so_set(unsigned int uhva_smf_cfg_wr_so_set);
int iSetHVA_SMF_WR_CFG_hva_smf_cfg_wrfna_thrld(unsigned int uhva_smf_cfg_wrfna_thrld);
int iSetHVA_SMF_WR_CFG_hva_smf_cfg_wrtype_thrld(unsigned int uhva_smf_cfg_wrtype_thrld);
int iSetHVA_SMF_WR_CFG_hva_smf_cfg_wrfa_thrld(unsigned int uhva_smf_cfg_wrfa_thrld);
int iSetHVA_SMF_WR_CFG_hva_smf_cfg_wr_fa_mode(unsigned int uhva_smf_cfg_wr_fa_mode);
int iSetHVA_SMF_WR_CFG_hva_smf_cfg_wr_fna_mode(unsigned int uhva_smf_cfg_wr_fna_mode);
int iSetHVA_SMF_WR_CFG_hva_smf_cfg_wr_fp_mode(unsigned int uhva_smf_cfg_wr_fp_mode);
int iSetHVA_SMF_WR_CFG_hva_smf_cfg_wr_type_mode(unsigned int uhva_smf_cfg_wr_type_mode);
int iSetHVA_SMF_WR_CFG_hva_smf_cfg_wr_so_mode(unsigned int uhva_smf_cfg_wr_so_mode);
int iSetHVA_SMF_ARSTRMID_hva_smf_rd_strmid(unsigned int uhva_smf_rd_strmid);
int iSetHVA_SMF_AWSTRMID_hva_smf_wr_strmid(unsigned int uhva_smf_wr_strmid);
int iSetHVA_SMF_PF_CMD_TYPE_hva_smf_cfg_pf_cmd_type(unsigned int uhva_smf_cfg_pf_cmd_type);
int iSetHVA_SMF_INT_STARUS_hva_smf_npq_ov_int_status(unsigned int uhva_smf_npq_ov_int_status);
int iSetHVA_SMF_INT_STARUS_hva_smf_npq_uf_int_status(unsigned int uhva_smf_npq_uf_int_status);
int iSetHVA_SMF_INT_STARUS_hva_smf_npq_send_empty_int_status(unsigned int uhva_smf_npq_send_empty_int_status);
int iSetHVA_SMF_INT_STARUS_hva_smf_pq_ov_int_status(unsigned int uhva_smf_pq_ov_int_status);
int iSetHVA_SMF_INT_STARUS_hva_smf_pq_uf_int_status(unsigned int uhva_smf_pq_uf_int_status);
int iSetHVA_SMF_INT_STARUS_hva_smf_pq_send_empty_int_status(unsigned int uhva_smf_pq_send_empty_int_status);
int iSetHVA_SMF_INT_STARUS_hva_smf_1bit_ecc_int_status(unsigned int uhva_smf_1bit_ecc_int_status);
int iSetHVA_SMF_INT_STARUS_hva_smf_2bit_ecc_int_status(unsigned int uhva_smf_2bit_ecc_int_status);
int iSetHVA_SMF_INT_STARUS_hva_cpth_fifo_ov_int_status(unsigned int uhva_cpth_fifo_ov_int_status);
int iSetHVA_SMF_INT_EN_hva_smf_npq_ov_int_en(unsigned int uhva_smf_npq_ov_int_en);
int iSetHVA_SMF_INT_EN_hva_smf_npq_uf_int_en(unsigned int uhva_smf_npq_uf_int_en);
int iSetHVA_SMF_INT_EN_hva_smf_npq_send_empty_int_en(unsigned int uhva_smf_npq_send_empty_int_en);
int iSetHVA_SMF_INT_EN_hva_smf_pq_ov_int_en(unsigned int uhva_smf_pq_ov_int_en);
int iSetHVA_SMF_INT_EN_hva_smf_pq_uf_int_en(unsigned int uhva_smf_pq_uf_int_en);
int iSetHVA_SMF_INT_EN_hva_smf_pq_send_empty_int_en(unsigned int uhva_smf_pq_send_empty_int_en);
int iSetHVA_SMF_INT_EN_hva_smf_1bit_ecc_int_en(unsigned int uhva_smf_1bit_ecc_int_en);
int iSetHVA_SMF_INT_EN_hva_smf_2bit_ecc_int_en(unsigned int uhva_smf_2bit_ecc_int_en);
int iSetHVA_SMF_INT_EN_hva_cpth_fifo_ov_int_en(unsigned int uhva_cpth_fifo_ov_int_en);
int iSetHVA_SMF_INT_SET_hva_smf_npq_ov_int_set(unsigned int uhva_smf_npq_ov_int_set);
int iSetHVA_SMF_INT_SET_hva_smf_npq_uf_int_set(unsigned int uhva_smf_npq_uf_int_set);
int iSetHVA_SMF_INT_SET_hva_smf_npq_send_empty_int_set(unsigned int uhva_smf_npq_send_empty_int_set);
int iSetHVA_SMF_INT_SET_hva_smf_pq_ov_int_set(unsigned int uhva_smf_pq_ov_int_set);
int iSetHVA_SMF_INT_SET_hva_smf_pq_uf_int_set(unsigned int uhva_smf_pq_uf_int_set);
int iSetHVA_SMF_INT_SET_hva_smf_pq_send_empty_int_set(unsigned int uhva_smf_pq_send_empty_int_set);
int iSetHVA_SMF_INT_SET_hva_smf_1bit_ecc_int_set(unsigned int uhva_smf_1bit_ecc_int_set);
int iSetHVA_SMF_INT_SET_hva_smf_2bit_ecc_int_set(unsigned int uhva_smf_2bit_ecc_int_set);
int iSetHVA_SMF_INT_SET_hva_cpth_fifo_ov_int_set(unsigned int uhva_cpth_fifo_ov_int_set);
int iSetHVA_SMF_INT_RAW_STATUS_hva_smf_npq_ov_int_raw_status(unsigned int uhva_smf_npq_ov_int_raw_status);
int iSetHVA_SMF_INT_RAW_STATUS_hva_smf_npq_uf_int_raw_status(unsigned int uhva_smf_npq_uf_int_raw_status);
int iSetHVA_SMF_INT_RAW_STATUS_hva_smf_npq_send_empty_int_raw_status(
    unsigned int uhva_smf_npq_send_empty_int_raw_status);
int iSetHVA_SMF_INT_RAW_STATUS_hva_smf_pq_ov_int_raw_status(unsigned int uhva_smf_pq_ov_int_raw_status);
int iSetHVA_SMF_INT_RAW_STATUS_hva_smf_pq_uf_int_raw_status(unsigned int uhva_smf_pq_uf_int_raw_status);
int iSetHVA_SMF_INT_RAW_STATUS_hva_smf_pq_send_empty_int_raw_status(unsigned int uhva_smf_pq_send_empty_int_raw_status);
int iSetHVA_SMF_INT_RAW_STATUS_hva_smf_1bit_ecc_int_raw_status(unsigned int uhva_smf_1bit_ecc_int_raw_status);
int iSetHVA_SMF_INT_RAW_STATUS_hva_smf_2bit_ecc_int_raw_status(unsigned int uhva_smf_2bit_ecc_int_raw_status);
int iSetHVA_SMF_INT_RAW_STATUS_hva_cpth_fifo_ov_int_raw_status(unsigned int uhva_cpth_fifo_ov_int_raw_status);
int iSetHVA_ICL_CFG_sc_dispatch_errrsp(unsigned int usc_dispatch_errrsp);
int iSetHVA_ICL_CFG_hva_icl_smmu_bdf(unsigned int uhva_icl_smmu_bdf);
int iSetHVA_SMF_AXI_MAX_TRANS_hva_smf_cfg_rd_max_trans(unsigned int uhva_smf_cfg_rd_max_trans);
int iSetHVA_SMF_AXI_MAX_TRANS_hva_smf_cfg_wr_max_trans(unsigned int uhva_smf_cfg_wr_max_trans);
int iSetHVA_SMF_CPI_CFG_hva_smf_cpi_10bit_tag_req_en(unsigned int uhva_smf_cpi_10bit_tag_req_en);
int iSetHVA_SMF_CPI_CFG_hva_smf_cpi_10bit_tag_cpl_en(unsigned int uhva_smf_cpi_10bit_tag_cpl_en);
int iSetHVA_SMF_CPI_CFG_hva_smf_cpi_extended_tag_en(unsigned int uhva_smf_cpi_extended_tag_en);
int iSetHVA_SMF_CPI_CFG_hva_smf_cpi_cpl_timeout_dis(unsigned int uhva_smf_cpi_cpl_timeout_dis);
int iSetHVA_SMF_CPI_CFG_hva_smf_cpi_cpl_timeout_value(unsigned int uhva_smf_cpi_cpl_timeout_value);
int iSetHVA_SMF_CPI_CFG_hva_smf_cpi_cfg_mrrs(unsigned int uhva_smf_cpi_cfg_mrrs);
int iSetHVA_SMF_CPI_CFG_hva_smf_cpi_cfg_mps(unsigned int uhva_smf_cpi_cfg_mps);
int iSetHVA_SMF_CPI_CFG_hva_smf_link_down(unsigned int uhva_smf_link_down);
int iSetHVA_SMF_CPI_CFG_hva_smf_cpi_tx_crd_active_en(unsigned int uhva_smf_cpi_tx_crd_active_en);
int iSetHVA_SMF_CPI_CRDT_CFG_hva_smf_cpi_p_hed_crdt(unsigned int uhva_smf_cpi_p_hed_crdt);
int iSetHVA_SMF_CPI_CRDT_CFG_hva_smf_cpi_p_dat_crdt(unsigned int uhva_smf_cpi_p_dat_crdt);
int iSetHVA_SMF_CPI_CRDT_CFG_hva_smf_cpi_np_hed_crdt(unsigned int uhva_smf_cpi_np_hed_crdt);
int iSetHVA_SMF_CPI_CRDT_CFG_hva_smf_cpi_crdt_init(unsigned int uhva_smf_cpi_crdt_init);
int iSetHVA_SMF_RAM_ECC_BYPASS_hva_smf_ram_err_chk_bypass(unsigned int uhva_smf_ram_err_chk_bypass);
int iSetHVA_SMF_RAM_ECC_ERR_INS_hva_smf_npq_db_ram_cerr_ins_req(unsigned int uhva_smf_npq_db_ram_cerr_ins_req);
int iSetHVA_SMF_RAM_ECC_ERR_INS_hva_smf_npq_db_ram_ucerr_ins_req(unsigned int uhva_smf_npq_db_ram_ucerr_ins_req);
int iSetHVA_SMF_RAM_ECC_ERR_INS_hva_smf_pq_db_ram_cerr_ins_req(unsigned int uhva_smf_pq_db_ram_cerr_ins_req);
int iSetHVA_SMF_RAM_ECC_ERR_INS_hva_smf_pq_db_ram_ucerr_ins_req(unsigned int uhva_smf_pq_db_ram_ucerr_ins_req);
int iSetHVA_SMF_RAM_ECC_ERR_INS_hva_smf_npq_entry_ram_cerr_ins_req(unsigned int uhva_smf_npq_entry_ram_cerr_ins_req);
int iSetHVA_SMF_RAM_ECC_ERR_INS_hva_smf_npq_entry_ram_ucerr_ins_req(unsigned int uhva_smf_npq_entry_ram_ucerr_ins_req);
int iSetHVA_SMF_RAM_ECC_ERR_INS_hva_smf_pq_entry_ram_cerr_ins_req(unsigned int uhva_smf_pq_entry_ram_cerr_ins_req);
int iSetHVA_SMF_RAM_ECC_ERR_INS_hva_smf_pq_entry_ram_ucerr_ins_req(unsigned int uhva_smf_pq_entry_ram_ucerr_ins_req);
int iSetHVA_SMF_RAM_ECC_ERR_INS_hva_cpth_fifo_ram_cerr_ins_req(unsigned int uhva_cpth_fifo_ram_cerr_ins_req);
int iSetHVA_SMF_RAM_ECC_ERR_INS_hva_cpth_fifo_ram_ucerr_ins_req(unsigned int uhva_cpth_fifo_ram_ucerr_ins_req);
int iSetHVA_SMF_FATAL_ERR_CTRL_hva_smf_npq_db_ram_ucerr_fatal_en(unsigned int uhva_smf_npq_db_ram_ucerr_fatal_en);
int iSetHVA_SMF_FATAL_ERR_CTRL_hva_smf_pq_db_ram_ucerr_fatal_en(unsigned int uhva_smf_pq_db_ram_ucerr_fatal_en);
int iSetHVA_SMF_FATAL_ERR_CTRL_hva_smf_npq_entry_ram_ucerr_fatal_en(unsigned int uhva_smf_npq_entry_ram_ucerr_fatal_en);
int iSetHVA_SMF_FATAL_ERR_CTRL_hva_smf_pq_entry_ram_ucerr_fatal_en(unsigned int uhva_smf_pq_entry_ram_ucerr_fatal_en);
int iSetHVA_SMF_FATAL_ERR_CTRL_hva_smf_npq_ov_fatal_en(unsigned int uhva_smf_npq_ov_fatal_en);
int iSetHVA_SMF_FATAL_ERR_CTRL_hva_smf_npq_uf_fatal_en(unsigned int uhva_smf_npq_uf_fatal_en);
int iSetHVA_SMF_FATAL_ERR_CTRL_hva_smf_npq_send_empty_fatal_en(unsigned int uhva_smf_npq_send_empty_fatal_en);
int iSetHVA_SMF_FATAL_ERR_CTRL_hva_smf_pq_ov_fatal_en(unsigned int uhva_smf_pq_ov_fatal_en);
int iSetHVA_SMF_FATAL_ERR_CTRL_hva_smf_pq_uf_fatal_en(unsigned int uhva_smf_pq_uf_fatal_en);
int iSetHVA_SMF_FATAL_ERR_CTRL_hva_smf_pq_send_empty_fatal_en(unsigned int uhva_smf_pq_send_empty_fatal_en);
int iSetHVA_SMF_FATAL_ERR_CTRL_hva_cpth_fifo_ram_ucerr_fatal_en(unsigned int uhva_cpth_fifo_ram_ucerr_fatal_en);
int iSetHVA_SMF_FATAL_ERR_CTRL_hva_cpth_fifo_ov_fatal_en(unsigned int uhva_cpth_fifo_ov_fatal_en);
int iSetHVA_SMF_FATAL_ERR_CTRL_hva_smf_fatal_err_en(unsigned int uhva_smf_fatal_err_en);
int iSetHVA_SMF_INNER_CRDT_hva_smf_inner_cpl_data_crdt(unsigned int uhva_smf_inner_cpl_data_crdt);
int iSetHVA_SMF_INNER_CRDT_hva_smf_inner_send_npq_crdt(unsigned int uhva_smf_inner_send_npq_crdt);
int iSetHVA_SMF_INNER_CRDT_hva_smf_inner_send_pq_crdt(unsigned int uhva_smf_inner_send_pq_crdt);
int iSetHVA_SMF_INNER_CRDT_hva_smf_inner_crdt_init(unsigned int uhva_smf_inner_crdt_init);
int iSetHVA_SMF_FIFO_AF_CFG_hva_smf_pq_sdata_fifo_af_th(unsigned int uhva_smf_pq_sdata_fifo_af_th);
int iSetHVA_SMF_CRDT_hva_smf_rsp_crdt(unsigned int uhva_smf_rsp_crdt);
int iSetHVA_SMF_CRDT_hva_smf_cpl_crdt(unsigned int uhva_smf_cpl_crdt);
int iSetHVA_SMF_CRDT_hva_smf_crdt_init(unsigned int uhva_smf_crdt_init);
int iSetHVA_SMF_PNP_ODR_DIS_hva_cpth_pnp_odr_dis(unsigned int uhva_cpth_pnp_odr_dis);
int iSetHVA_SMF_DFX_CFG_hva_smf_dfx_tx_cpl_stat_en(unsigned int uhva_smf_dfx_tx_cpl_stat_en);
int iSetHVA_SMF_DFX_CFG_hva_smf_dfx_tx_cpl_stat_clr(unsigned int uhva_smf_dfx_tx_cpl_stat_clr);
int iSetHVA_SMF_DFX_CFG_hva_smf_dfx_tx_cpl_cnt_clr(unsigned int uhva_smf_dfx_tx_cpl_cnt_clr);
int iSetHVA_SMF_DFX_CFG_hva_smf_dfx_hva_get_cpi_p_cnt_clr(unsigned int uhva_smf_dfx_hva_get_cpi_p_cnt_clr);
int iSetHVA_SMF_DFX_CFG_hva_smf_dfx_tx_p_stat_en(unsigned int uhva_smf_dfx_tx_p_stat_en);
int iSetHVA_SMF_DFX_CFG_hva_smf_dfx_tx_p_stat_clr(unsigned int uhva_smf_dfx_tx_p_stat_clr);
int iSetHVA_SMF_DFX_CFG_hva_smf_dfx_ucerr_cnt_clr(unsigned int uhva_smf_dfx_ucerr_cnt_clr);
int iSetHVA_SMF_DFX_CFG_hva_smf_dfx_cerr_cnt_clr(unsigned int uhva_smf_dfx_cerr_cnt_clr);
int iSetHVA_SMF_DFX_CPL_BW0_hva_smf_dfx_tx_cpl_bw_curr(unsigned int uhva_smf_dfx_tx_cpl_bw_curr);
int iSetHVA_SMF_DFX_CPL_BW0_hva_smf_dfx_tx_cpl_bw_max(unsigned int uhva_smf_dfx_tx_cpl_bw_max);
int iSetHVA_SMF_DFX_CPL_BW1_hva_smf_dfx_tx_cpl_bw_ava(unsigned int uhva_smf_dfx_tx_cpl_bw_ava);
int iSetHVA_SMF_DFX_NPQ_DB_STATE_hva_smf_dfx_npq_db_state(unsigned int uhva_smf_dfx_npq_db_state);
int iSetHVA_SMF_DFX_TX_CPL_CNT0_hva_smf_dfx_tx_cpl_dat_err_cnt(unsigned int uhva_smf_dfx_tx_cpl_dat_err_cnt);
int iSetHVA_SMF_DFX_TX_CPL_CNT0_hva_smf_dfx_tx_cpl_unsuccess_cnt(unsigned int uhva_smf_dfx_tx_cpl_unsuccess_cnt);
int iSetHVA_SMF_DFX_TX_CPL_CNT1_hva_smf_dfx_tx_cpl_cnt(unsigned int uhva_smf_dfx_tx_cpl_cnt);
int iSetHVA_SMF_NPQ_PTR_hva_smf_dfx_npq_send_ptr(unsigned int uhva_smf_dfx_npq_send_ptr);
int iSetHVA_SMF_NPQ_PTR_hva_smf_dfx_npq_free_ptr(unsigned int uhva_smf_dfx_npq_free_ptr);
int iSetHVA_SMF_NPQ_PTR_hva_smf_dfx_npq_rls_ptr(unsigned int uhva_smf_dfx_npq_rls_ptr);
int iSetHVA_SMF_NPQ_PTR_hva_smf_dfx_npq_free_cnt(unsigned int uhva_smf_dfx_npq_free_cnt);
int iSetHVA_SMF_DFX_P_BW0_hva_smf_dfx_tx_p_bw_curr(unsigned int uhva_smf_dfx_tx_p_bw_curr);
int iSetHVA_SMF_DFX_P_BW0_hva_smf_dfx_tx_p_bw_max(unsigned int uhva_smf_dfx_tx_p_bw_max);
int iSetHVA_SMF_DFX_P_BW1_hva_smf_dfx_tx_p_bw_ava(unsigned int uhva_smf_dfx_tx_p_bw_ava);
int iSetHVA_SMF_DFX_P_CNT_hva_smf_dfx_hva_get_cpi_p_cnt(unsigned int uhva_smf_dfx_hva_get_cpi_p_cnt);
int iSetHVA_SMF_DFX_PQ_PTR_hva_smf_dfx_pq_send_ptr(unsigned int uhva_smf_dfx_pq_send_ptr);
int iSetHVA_SMF_DFX_PQ_PTR_hva_smf_dfx_pq_free_ptr(unsigned int uhva_smf_dfx_pq_free_ptr);
int iSetHVA_SMF_DFX_PQ_PTR_hva_smf_dfx_pq_rls_ptr(unsigned int uhva_smf_dfx_pq_rls_ptr);
int iSetHVA_SMF_DFX_PQ_PTR_hva_smf_dfx_pq_free_cnt(unsigned int uhva_smf_dfx_pq_free_cnt);
int iSetHVA_SMF_DFX_PQ_WR_ERR_hva_smf_dfx_pq_wr_err_abresp(unsigned int uhva_smf_dfx_pq_wr_err_abresp);
int iSetHVA_SMF_DFX_PQ_WR_ERR_hva_smf_dfx_pq_wr_err(unsigned int uhva_smf_dfx_pq_wr_err);
int iSetHVA_SMF_DFX_PQ_WR_ERR_hva_smf_dfx_pq_wr_err_clr(unsigned int uhva_smf_dfx_pq_wr_err_clr);
int iSetHVA_SMF_DFX_PQ_WR_ERR_ADDR_H_hva_smf_dfx_pq_wr_err_addr_h(unsigned int uhva_smf_dfx_pq_wr_err_addr_h);
int iSetHVA_SMF_DFX_PQ_WR_ERR_ADDR_L_hva_smf_dfx_pq_wr_err_addr_l(unsigned int uhva_smf_dfx_pq_wr_err_addr_l);
int iSetHVA_SMF_DFX_TLP_ZERO_LEN_hva_smf_dfx_pq_zero_write(unsigned int uhva_smf_dfx_pq_zero_write);
int iSetHVA_SMF_DFX_TLP_ZERO_LEN_hva_smf_dfx_npq_zero_read(unsigned int uhva_smf_dfx_npq_zero_read);
int iSetHVA_SMF_DFX_AXI_BID_ERR_hva_smf_dfx_hva_bid_err(unsigned int uhva_smf_dfx_hva_bid_err);
int iSetHVA_SMF_DFX_DB_ECC_ERR_ADDR_hva_smf_dfx_pq_db_ecc_err_addr(unsigned int uhva_smf_dfx_pq_db_ecc_err_addr);
int iSetHVA_SMF_DFX_DB_ECC_ERR_ADDR_hva_smf_dfx_npq_db_ecc_err_addr(unsigned int uhva_smf_dfx_npq_db_ecc_err_addr);
int iSetHVA_SMF_DFX_ENTRY_ECC_ERR_ADDR_hva_smf_dfx_pq_entry_ecc_err_addr(
    unsigned int uhva_smf_dfx_pq_entry_ecc_err_addr);
int iSetHVA_SMF_DFX_ENTRY_ECC_ERR_ADDR_hva_smf_dfx_npq_entry_ecc_err_addr(
    unsigned int uhva_smf_dfx_npq_entry_ecc_err_addr);
int iSetHVA_SMF_DFX_ENTRY_ECC_ERR_ADDR_hva_smf_dfx_cpth_fifo_ecc_err_addr(
    unsigned int uhva_smf_dfx_cpth_fifo_ecc_err_addr);
int iSetHVA_SMF_DFX_MEM_CERR_CNT_hva_smf_dfx_mem_cerr_cnt(unsigned int uhva_smf_dfx_mem_cerr_cnt);
int iSetHVA_SMF_DFX_MEM_UCERR_CNT_hva_smf_dfx_mem_ucerr_cnt(unsigned int uhva_smf_dfx_mem_ucerr_cnt);
int iSetHVA_SMF_DFX_ECC_STA_hva_smf_npq_db_ram_cerr(unsigned int uhva_smf_npq_db_ram_cerr);
int iSetHVA_SMF_DFX_ECC_STA_hva_smf_npq_db_ram_ucerr(unsigned int uhva_smf_npq_db_ram_ucerr);
int iSetHVA_SMF_DFX_ECC_STA_hva_smf_pq_db_ram_cerr(unsigned int uhva_smf_pq_db_ram_cerr);
int iSetHVA_SMF_DFX_ECC_STA_hva_smf_pq_db_ram_ucerr(unsigned int uhva_smf_pq_db_ram_ucerr);
int iSetHVA_SMF_DFX_ECC_STA_hva_smf_npq_entry_ram_cerr(unsigned int uhva_smf_npq_entry_ram_cerr);
int iSetHVA_SMF_DFX_ECC_STA_hva_smf_npq_entry_ram_ucerr(unsigned int uhva_smf_npq_entry_ram_ucerr);
int iSetHVA_SMF_DFX_ECC_STA_hva_smf_pq_entry_ram_cerr(unsigned int uhva_smf_pq_entry_ram_cerr);
int iSetHVA_SMF_DFX_ECC_STA_hva_smf_pq_entry_ram_ucerr(unsigned int uhva_smf_pq_entry_ram_ucerr);
int iSetHVA_SMF_DFX_ECC_STA_hva_cpth_fifo_ram_cerr(unsigned int uhva_cpth_fifo_ram_cerr);
int iSetHVA_SMF_DFX_ECC_STA_hva_cpth_fifo_ram_ucerr(unsigned int uhva_cpth_fifo_ram_ucerr);
int iSetHVA_SMF_MEM_CTRL_BUS_0_hva_smf_mem_ctrl_bus_0(unsigned int uhva_smf_mem_ctrl_bus_0);
int iSetHVA_SMF_MEM_CTRL_BUS_1_hva_smf_mem_ctrl_bus_1(unsigned int uhva_smf_mem_ctrl_bus_1);
int iSetHVA_SMF_MEM_CTRL_BUS_2_hva_smf_mem_ctrl_bus_2(unsigned int uhva_smf_mem_ctrl_bus_2);
int iSetHVA_SMF_MEM_CTRL_BUS_3_hva_smf_mem_ctrl_bus_3(unsigned int uhva_smf_mem_ctrl_bus_3);
int iSetHVA_SMF_MEM_CTRL_BUS_4_hva_smf_mem_ctrl_bus_4(unsigned int uhva_smf_mem_ctrl_bus_4);
int iSetSMF_HVA_REQ_API_NUM_dfx_smf_hva_wr_requs_cnt(unsigned int udfx_smf_hva_wr_requs_cnt);
int iSetSMF_HVA_REQ_API_NUM_dfx_smf_hva_rd_requs_cnt(unsigned int udfx_smf_hva_rd_requs_cnt);
int iSetHVA_SMF_RSP_API_NUM_dfx_hva_smf_rd_rsp_cnt(unsigned int udfx_hva_smf_rd_rsp_cnt);
int iSetHVA_SMMU_AXI_RD_NUM_dfx_smmu_hva_rl_cnt(unsigned int udfx_smmu_hva_rl_cnt);
int iSetHVA_SMMU_AXI_RD_NUM_dfx_hva_smmu_ar_cnt(unsigned int udfx_hva_smmu_ar_cnt);
int iSetHVA_SMMU_AXI_WR_NUM_dfx_hva_smmu_wl_cnt(unsigned int udfx_hva_smmu_wl_cnt);
int iSetHVA_SMMU_AXI_WR_NUM_dfx_hva_smmu_aw_cnt(unsigned int udfx_hva_smmu_aw_cnt);
int iSetSMMU_HVA_AXI_B_NUM_dfx_smmu_hva_b_cnt(unsigned int udfx_smmu_hva_b_cnt);
int iSetHVA_LAT_STS_CFG_cfg_lat_stat_clr(unsigned int ucfg_lat_stat_clr);
int iSetHVA_LAT_STS_CFG_cfg_lat_stat_en(unsigned int ucfg_lat_stat_en);
int iSetHVA_WR_BP_CFG_cfg_wr_bp_clr_th(unsigned int ucfg_wr_bp_clr_th);
int iSetHVA_WR_BP_CFG_cfg_wr_bp_th(unsigned int ucfg_wr_bp_th);
int iSetHVA_RD_BP_CFG_cfg_rd_bp_clr_th(unsigned int ucfg_rd_bp_clr_th);
int iSetHVA_RD_BP_CFG_cfg_rd_bp_th(unsigned int ucfg_rd_bp_th);
int iSetHVA_JAM_TIME_CFG_cfg_jam_bp_bus_timer(unsigned int ucfg_jam_bp_bus_timer);


#endif // HI1823_C_UNION_DEFINE_H
